1. Field of the Invention
The present invention relates in general to MLC substrates for packaging electronic devices, and more particularly, to methods and structures with electrical wiring having regions of larger wire cross-sectional areas in those locations where the package must supply higher current distribution to the electronic devices and/or where signal lines need lower electrical resistance.
2. Description of Related Art
In the ceramic electronics industry, multilayer ceramic (MLC) technology is typically used to create three-dimensional circuitry for microelectronic devices such as integrated circuits and ceramic capacitors. These three-dimensional circuitries are made by applying a conductive material in a circuit pattern on a ceramic/polymer composite sheet known as a green sheet.
A green sheet may have a number of via holes punched in it to allow vertical connection between the conductive material on adjacent sheets, whereby after the vias are punched in the sheets, the green sheet is screened and patterned by applying a conductive paste into the via holes and along the surface of the green sheet. A number of via punched and screened green sheets are then stacked in a designated order and laminated together under appropriate heat and pressure to form a laminate which can be handled as a unified structure. The laminated ceramic/polymer composite is heated to remove the polymer, and then heated to a higher temperature to sinter and densify the ceramic, thereby forming the final MLC.
Over the years, generations of MLC technology have developed to incorporate advanced technologies, including, reduced grid and feature dimensions to satisfy the needs of advanced integrated circuits, IC's, of continuously increasing complexity, that require increasing interconnection capability, higher interconnection density, higher power density, and operate at increasingly higher frequency. Yet, these ever shrinking state of the art packages carry with them the problem of limited current carrying capability, which in turn, leads to an undesirable increase in resistance across the electronic package.
Current capability is a function of the metal wiring type and line width, as well as the thickness and line length of the wire. In electronic packaging, the wiring line width and thickness are typically dependent on the technology used to build the package. For instance, in both MLC and organic packaging, such wiring dimensions are designed by the manufacturing process utilized to build the MLC or organic package. In addition, wire dimensions limit the maximum size of an electronic package mainly because the wire maximum length defines the wire total resistance and this total resistance is always specified to given maximum, usually in the 2 to 4 Ohms. But the package size also has impact on the package interconnecting capability, defined as the maximum number of independent signal lines that a given package can provide to interconnect between a point on the package top surface and the package bottom surface. This package interconnecting capability is typically proportional to the package surface area, and a function of the minimum spacing between surface electrical interconnecting pads, or I/O's.
Yet, with advanced electronic packaging technologies, the dimensions and operating voltages thereof continually diminish in size while the requirements of local current densities for power distribution and/or reduced line resistance for signal wiring continue to increase. This combined need for an increase in power dissipation within a smaller packaging component poses significant problems in the fabrication of such packages, as well as imposes restrictions on feature tolerances and maintaining a tolerable resistance
As future generations of electronic packages are required to have reduced grid and feature dimensions and increased power density, this grid reduction drives the need for improved approaches of reducing resistance. As such, a need continues to exist in the art for faster electronic packages having increased interconnecting capability, smaller features, reduced resistance, and methods for forming the same.